Browsing by Author "Deepak Agarwal"
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Item Exploiting Application-Level Information to Reduce Memory Bandwidth Consumption(2001-12-17) Deepak Agarwal; Donald YeungAs processors continue to deliver ever higher levels of performance and as memory latency tolerance techniques become widespread to address the increasing cost of accessing memory, memory bandwidth will emerge as a major limitation to continued increases in application performance. In this paper, we propose a hybrid hardware/software technique for addressing the memory bandwidth bottleneck by more intelligently transferring data between the memory system and cache. Our approach uses off-line analysis of the source code and special annotated memory instructions to convey spatial locality information to the hardware at runtime. The memory system uses this information to fetch only the data that will be accessed by the program--data that is unlikely to be referenced is not fetched, hence reducing the application's memory traffic. Our technique uses modified sectored caches to fetch and cache the variable-sized fine-grained data accessed through annotated memory instructions. Our results show that annotated memory instructions remove between 20\% and 59\% of the cache traffic for 7 applications. Furthermore, annotated memory instructions achieve a 13\% performance gain on a cycle-accurate simulator when used alone, and a 26.4\% performance gain when combined with software prefetching, compared to a 2.3\% performance degradation when prefetching with normal memory instructions. This has been replaced by CS-TR-4384. (Also referenced as UMIACS-TR-2001-81)Item Exploiting Application-Level Information to Reduce Memory Bandwidth Consumption(2002-08-01) Deepak Agarwal; Donald Yeungs processors continue to deliver higher levels of performance and as memory latency toler-ance techniques become widespread to address the increasing cost of accessing memory, memory bandwidth will emerge as a major performance bottleneck. Rather than rely solely on widerand faster memories to address memory bandwidth shortages, an alternative is to use existing memory bandwidth more efficiently. A promising approach is hardware-based selective sub-blocking. In this technique, hardware predictors track the portions of cache blocks that are referenced by the processor. On a cache miss, the predictors are consulted and only previ-ously referenced portions are fetched into the cache, thus conserving memory bandwidth. This paper proposes a software-centric approch to selective sub-blocking. We make the keyobservation that wasteful data fetching inside long cache blocks arises due to certain sparse memory references, and that such memory references can be identified in the application sourcecode. Rather than use hardware predictors to discover sparse memory reference patterns from the dynamic memory reference stream, our approach relies on the programmer or compiler toidentify the sparse memory references statically, and to use special annotated memory instructions to specify the amount of spatial reuse associated with such memory references. At runtime,the size annotations select the amount of data to fetch on each cache miss, thus fetching only data that will likely be accessed by the processor. Our results show annotated memory instruc-tions remove between 54% and 71% of cache traffic for 7 applications, reducing more traffic than hardware selective sub-blocking using a 32 Kbyte predictor on all applications, and reducingas much traffic as hardware selective sub-blocking using an 8 Mbyte predictor on 5 out of 7 applications. Overall, annotated memory instructions achieve a 17% performance gain whenused alone, and a 22.3% performance gain when combined with software prefetching, compared to a 7.2% performance degradation when prefetching without annotated memory instructions. This is an updated version of CS-TR-4304. Also UMIACS-TR-2002-64