Tang, C.F.T.Liu, K.J. RayTretter, S.A.In this paper we present systolic algorithms and architectures for parallel and fully-pipelined instantaneous optimal weight extraction for multiple sidelobe canceller (MSC) and minimum variance distortionless response (MVDR) beamformer. The proposed systolic parallelogram array processors are parallel and fully pipelined, and they can extract the optimal weights instantaneously without the need for forward or backward substitution. We also show that the square-root-free Givens method can be easily incorporated to improve the throughput rate and speed up the system. As a result, these MSC and MVDR systolic array weight extraction systems are suitable for real- time VLSI implementation in practical radar/sonar systems.en-USsignal processingparallel architecturesVLSI architecturesSystems IntegrationTechnical Report