Chao, C-Y.Lin, H-J.Milor, LindaAnalog circuits are usually tested by checking if their specifications are satisfied. This methodology is very costly. We attempt to reduce production testing time by presecuting a fault- driven methodology to handle LSI analog circuits in this paper. A fault-driven methodology has to be able to detect both parametric and catastrophic faults. For statistical performance simulation to detect parametric faults, we propose a two level approach because of the high cost of simulating LSI analog circuits statistically, where a set of primary statistical variables are first mapped to block performances by empirical models, derived by statistical regression techniques and then mapped to system performances using a behavioral simulator. For catastrophic fault simulation, open and short circuits are mapped to distortions in block performances by simulation and then mapped to system performances using a behavioral simulator. Using our statistical simulation technique for parametric variations and our fault simulation technique for catastrophic faults, we will minimize testing time using the algorithm in [1] by eliminating unnecessary specification tests and optimizing the order of tests. The effectiveness and fault coverage of block level testing are also investigated.en-UScomputer aided designcomputer aided manufacturingmeasurementsSystems IntegrationTechnical Report