Iyer, BharathThe use of VLIW architecture has become widespread in the DSP arena due to the combined benefits of simple hardware and instruction level parallelism extracted by the compiler. In an attempt to extract higher processing throughput we investigate simultaneous multithreading (SMT) to exploit thread-level parallelism in a VLIW DSP. We propose an extended split-issue mechanism that allows us to break the instruction packet syntax of a VLIW compiler without violating the dataflow dependences. The capability to break VLIW instruction packets gives us greater freedom in scheduling instructions from different threads based on functional unit availability. We find that the SMT VLIW DSP provides significant processing throughput gains, which could also be traded-off for rich energy savings. The extended split-issue mechanism also provides us with an unprecedented, albeit limited, degree of freedom in disassociating the hardware implementation of the VLIW processor with the instruction set architecture (ISA). Simulation results show that the ability to modify the hardware implementation based on the utilisation statistics presents a new dimension that can be exploited to improve the efficiency of the processor.en-USThesisEngineering, Electronics and Electrical