HWANG, YU-CHULElectrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of advanced device technologies. This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques. The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFETs after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared. To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using a thermal RC network was developed. A correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of the square pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well.en-USDissertationEngineering, Mechanical