Software-Managed Address Translation
| dc.contributor.author | Jacob, Bruce | |
| dc.contributor.author | Mudge, Trevor | |
| dc.date.accessioned | 2007-11-08T18:51:23Z | |
| dc.date.available | 2007-11-08T18:51:23Z | |
| dc.date.issued | 1997-02 | |
| dc.description.abstract | In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that software-managed address translation is just as efficient as hardware- managed address translation, and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms. | en |
| dc.format.extent | 92990 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | "Software-managed address translation." Bruce L Jacob and Trevor N Mudge. Proc. Third International Symposium on High Performance Computer Architecture (HPCA'97), pp. 156-167, San Antonio TX, February 1997. | en |
| dc.identifier.uri | http://hdl.handle.net/1903/7467 | |
| dc.language.iso | en_US | en |
| dc.relation.isAvailableAt | A. James Clark School of Engineering | en_us |
| dc.relation.isAvailableAt | Electrical & Computer Engineering | en_us |
| dc.relation.isAvailableAt | Digital Repository at the University of Maryland | en_us |
| dc.relation.isAvailableAt | University of Maryland (College Park, MD) | en_us |
| dc.subject | software-managed address translation | en |
| dc.subject | memory management | en |
| dc.title | Software-Managed Address Translation | en |
| dc.type | Presentation | en |