VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression
| dc.contributor.author | Yu, S-S. | en_US |
| dc.contributor.author | Kolagotla, Ravi K. | en_US |
| dc.contributor.author | JaJa, Joseph F. | en_US |
| dc.contributor.department | ISR | en_US |
| dc.date.accessioned | 2007-05-23T09:50:40Z | |
| dc.date.available | 2007-05-23T09:50:40Z | |
| dc.date.issued | 1992 | en_US |
| dc.description.abstract | We describe a pipelined systolic architecture for implementing predictive Tree-Searched Vector Quantization (PTSVQ) for real- time image and speech coding applications. This architecture uses identical processors for both the encoding and decoding processes. the overall design is regular and the control is simple. Input data is processed at a rate of 1 pixel per clock cycle, which allows real-time processing of images at video rates. We implemented these processors using 1.2um CMOS technology. Spice simulations indicate correct operation at 40 MHz. Prototype version of these chips fabricated using 2um CMOS technology work at 20 MHz. | en_US |
| dc.format.extent | 1276907 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1903/5230 | |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | ISR; TR 1992-48 | en_US |
| dc.subject | data compression | en_US |
| dc.subject | image processing | en_US |
| dc.subject | signal processing | en_US |
| dc.subject | speech processing | en_US |
| dc.subject | vector quantization | en_US |
| dc.subject | VLSI architectures | en_US |
| dc.subject | systolic architecture | en_US |
| dc.subject | Systems Integration | en_US |
| dc.title | VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression | en_US |
| dc.type | Technical Report | en_US |
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