Cache Design for Embedded Real-Time Systems

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dc.contributor.authorJacob, Bruce
dc.date.accessioned2007-10-25T18:41:23Z
dc.date.available2007-10-25T18:41:23Z
dc.date.issued1999-06-30
dc.description.abstractCaches have long been a mechanism for speeding memory access and are popular in embedded hardware architectures from microcontrollers to core-based ASIC designs. However, caches are considered ill-suited for embedded real-time systems because they provide a probabilistic performance boost— a cache may or may not contain the desired data at any given moment. Analysis that guarantees when an item will or will not be in the cache has proven difficult, so many real-time systems simply disable caching and schedule tasks based on worst-case memory access time. Yet there are several cache organizations that provide the benefit of caching without the real-time drawbacks of hardware-managed caches. These are software-managed caches, and several different examples can be found, from DSP-style on-chip RAM to academic designs. This paper compares the operation and organization of caches as found in general-purpose processors, microcontrollers, and DSPs; it also discusses designs for embedded realtime systems.en
dc.format.extent209692 bytes
dc.format.extent42782 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.identifier.citation"Cache design for embedded real-time systems." Bruce L Jacob. Embedded Systems Conference, Summer 1999. Danvers MA, June 1999.en
dc.identifier.urihttp://hdl.handle.net/1903/7441
dc.language.isoen_USen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.subjectcacheen
dc.subjectgeneral-purpose processorsen
dc.subjectmicrocontrollersen
dc.subjectDSPsen
dc.titleCache Design for Embedded Real-Time Systemsen
dc.typePresentationen

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