Performance Characteristics of an Intelligent Memory System

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dc.contributor.advisorSilio, Charlesen_US
dc.contributor.authorTeller, Justin Stevensonen_US
dc.contributor.departmentElectrical Engineeringen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.date.accessioned2004-08-27T05:20:22Z
dc.date.available2004-08-27T05:20:22Z
dc.date.issued2004-07-07en_US
dc.description.abstractThe memory system is increasingly becoming a performance bottleneck. Several intelligent memory systems, such as the ActivePages, DIVA, and IRAM architectures, have been proposed to alleviate the processor-memory bottleneck. This thesis presents the Memory Arithmetic Unit and Interface (MAUI) architecture. The MAUI architecture combines ideas of the ActivePages, DIVA, and ULMT architectures into a new intelligent memory system. A simulator of the MAUI architecture was added to the SimpleScalar v4.0 toolset. Simulation results indicate that the MAUI architecture provides the largest application speedup when operating on datasets that are much too large to fit in the processor's cache and when integrated with systems using a high performance DRAM system and a low performance processor. By coupling a 2000 MHz processor with an 800 MHz DRDRAM DRAM system, the Stream benchmark, originally written by John D. McCalpin, completed 121% faster in simulations when optimized to use the MAUI architecture.en_US
dc.format.extent868300 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/1903/1724
dc.language.isoen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledIntelligent Memory Systemen_US
dc.subject.pquncontrolledMAUIen_US
dc.subject.pquncontrolledSimpleScalaren_US
dc.subject.pquncontrolledcomputer architectureen_US
dc.subject.pquncontrolledmemory system architectureen_US
dc.titlePerformance Characteristics of an Intelligent Memory Systemen_US
dc.typeThesisen_US

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