VLSI Implemented ML Joint Carrier Phase and Timing Offsets Joint Estimator for QPSK/QQPSK Burst Modems

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1999

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A high performance ASIC supporting multiple modulation, error correction, and frame formats is under development at Hughes Network Systems, Inc. Powerful and generic data-aided (DA) estimators are needed to accommodate operation in the required modes. In this paper, a simplified DA maximum likelihood (ML) joint estimator for carrier phase and symbol timing offset for QPSK/OQPSK burst modems and a sample systolic VLSI implementation for the estimator are presented.

Furthermore, the Cramer-Rao lower bound (CRLB) for DA case is investigated. The performance of the estimator is shown through simulation to meet the CRLB even at low signal-to-noise ratios (SNR). Compared with theoretical solutions, the proposed estimator is less computationally intensive and is therefore easier to implement using current VLSI technology. IEEE Wireless Communications and Networking Conference: WCNC'99

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