DRAMsim: A Memory System Simulator

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dc.contributor.authorWang, David
dc.contributor.authorGanesh, Brinda
dc.contributor.authorTuaycharoen, Nuengwong
dc.contributor.authorBaynes, Kathleen
dc.contributor.authorJaleel, Aamer
dc.contributor.authorJacob, Bruce
dc.date.accessioned2007-10-31T14:28:25Z
dc.date.available2007-10-31T14:28:25Z
dc.date.issued2005-09
dc.description.abstractAs memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly important. With the trend to develop multi-threaded, multi-core processors, the demands on the memory system will continue to scale. However, determining the optimal memory system configuration is non-trivial. The memory system performance is sensitive to a large number of parameters. Each of these parameters take on a number of values and interact in fashions that make overall trends difficult to discern. A comparison of the memory system architectures becomes even harder when we add the dimensions of power consumption and manufacturing cost. Unfortunately, there is a lack of tools in the public-domain that support such studies. Therefore, we introduce DRAMsim, a detailed and highly configurable C-based memory system simulator to fill this gap. DRAMsim implements detailed timing models for a variety of existing memories, including SDRAM, DDR, DDR2, DRDRAM and FB-DIMM, with the capability to easily vary their parameters. It also models the power consumption of SDRAM and its derivatives. It can be used as a standalone simulator or as part of a more comprehensive system-level model. We have successfully integrated DRAMsim into a variety of simulators including MASE[15], Sim-alpha[14], BOCHS[2] and GEMS[13]. The simulator can be downloaded from www.ece.umd.edu/dramsim.en
dc.format.extent220930 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citation"DRAMsim: A memory-system simulator." David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Katie Baynes, Aamer Jaleel, and Bruce Jacob. SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 100-107. September 2005.en
dc.identifier.urihttp://hdl.handle.net/1903/7444
dc.language.isoen_USen
dc.publisherACM (Association for Computing Machinery) Publicationsen
dc.relation.isAvailableAtA. James Clark School of Engineeringen_us
dc.relation.isAvailableAtElectrical & Computer Engineeringen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us
dc.rights.licenseDOI: http://doi.acm.org/10.1145/1105734.1105748
dc.subjectDRAMsimen
dc.subjectC-based memory system simulatoren
dc.subjectmemory systemen
dc.subjectDRAMen
dc.titleDRAMsim: A Memory System Simulatoren
dc.typeArticleen

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