INTEGRATED THERMAL MANAGEMENT OF HIGH-POWER ELECTRONICS: FROM DIE-LEVEL DESIGNS TO COMPONENT-LEVEL TWO-PHASE COOLING.

Abstract

Thermal management has become a critical challenge in modern semiconductor devices as increasing power densities push the limits of conventional cooling technologies. Rapid advances in electronic technologies, including artificial intelligence (AI)-driven computing workloads, high-performance computing (HPC) platforms, wireless and radio-frequency (RF) communication systems, power electronics, and photonic devices, are significantly increasing heat generation in semiconductor devices. These challenges are particularly pronounced in emerging high-power and high-frequency applications, where advanced semiconductor materials and device architectures introduce significant thermal constraints. Consequently, effective thermal management strategies must be developed across multiple levels, from the transistor to the component scale. This dissertation addresses these challenges by focusing on two key domains:die-level thermal management and component-level cooling. The first part of this dissertation focuses on die-level thermal management to mitigate self-heating in AlₓGaN₁₋ₓ ultra-wide bandgap (UWBG) devices for high-power RF applications. While AlGaN devices offer significant advantages due to their wide bandgap (>5 eV) and high breakdown electric field, their relatively low thermal conductivity leads to high thermal resistance and severe self-heating. This work investigates the effects of device architecture on the thermal performance of AlGaN UWBG devices. Specifically, it examines the impact of channel and substrate engineering through both numerical and experimental studies under steady-state and transient operation. Gate resistance thermometry (GRT) and transient thermoreflectance imaging (TRI) techniques are employed for thermal characterization. Experimental results show that integrating a high thermal conductivity AlN substrate with a thin AlGaN channel (5 nm) significantly enhances heat dissipation. The combined effect of improved heat spreading through the high-k substrate and reduced channel thickness results in a record-low thermal resistance of <4 K·mm/W. This represents an ≈90% reduction compared with thicker-channel (500 nm) HEMT devices on sapphire substrates and yields performance comparable to state-of-the-art (SOA) GaN-on-SiC technologies. Additional studies on polarization-graded FET architectures further demonstrate improved thermal resistance through channel morphology engineering. The second part of this dissertation addresses component-level thermal management by developing a novel two-phase direct-to-chip evaporative cooling (DCEC) technology based on hollow micropillars. The operating principle leverages the energy barrier created by the sharp edges of the micropillars, known as the canthotaxis (edge) effect, to confine droplets atop the structures. To understand the underlying physics, single-droplet studies are conducted to examine how droplet morphology and surface parameters affect thermal performance. Insights from these studies guide the development of device-level numerical models and proof-of-concept experimental devices comprising arrays of hollow micropillars. The resulting DCEC system consists of a liquid delivery layer (LDL) at the base and arrays of hollow micropillars on top. In operation, the coolant is actively pumped through the LDL and delivered into the hollow micropillars, where it forms either a concave or convex meniscus, or floods the evaporator depending on the operating pressure. To systematically evaluate this behavior, a parametric study is conducted for water and refrigerants (Opteon™ 2P50 and R-1336mzz(Z)) by varying substrate temperature, contact angle, micropillar pitch, pillar dimensions, and liquid expansion regimes. The analysis reveals that liquid expansion behavior within the micropillars strongly influences thermal performance. In particular, droplet confinement at the outer edge of the micropillars yields up to 3× higher heat transfer compared with regimes in which the liquid meniscus remains suspended inside the hollow micropillar cavity. Accordingly, theoretical heat fluxes of 575 W/cm² and 413 W/cm² are achievable under optimized conditions using water and R-1336mzz(Z), respectively. In addition, pressure analysis is performed to determine the required inlet pressure for stable operation across different regimes. Based on these findings, a microscale evaporator prototype is fabricated using silicon microfabrication techniques. Experiments are conducted in a custom-built environmental chamber under controlled conditions using DI water as the coolant. The results demonstrate the operating principles of the evaporator, in which hollow micropillars promote thin liquid-film formation at moderate heat fluxes and enable efficient vapor venting at higher heat fluxes. The device achieves a maximum heat transfer coefficient of 1 × 10⁵ W/m²·K while maintaining an area-normalized thermal resistance below 0.1 cm²·K/W, with 5× lower pumping power than state-of-the-art (SOA) single-phase cooling technologies. To further elucidate the operating mechanisms of DCEC, additional visualization studies are conducted. Overall, this dissertation establishes a comprehensive thermal management framework that spans transistor-level thermal engineering and component-level cooling, enabled by advanced two-phase architectures. By addressing thermal challenges at two critical stages of the semiconductor thermal pathway, this work demonstrates how coordinated optimization across multiple levels of the thermal hierarchy can significantly enhance heat dissipation in high-power electronic devices. These results provide new insights and scalable design strategies for the thermal management of next-generation high-power and high-density electronic systems.