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Eliminating Inter-proces Cache Interference Through Reconfigurability for Real-time and Low Power Embedded Systems

dc.contributor.advisorPetrov, Peteren_US
dc.contributor.authorReddy, Rakeshen_US
dc.description.abstractThis study proposes a technique which leverages data cache reconfigurability to address the problem of cache interference in multitasking embedded systems. Modern embedded systems often implement complex applications, comprising of multiple execution tasks with heavy memory requirements. Data caches are necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. Cache outcomes in multi-tasking environments are difficult to predict, thus resulting in very poor real-time performance guarantees. Additionally, caches contribute to a significant amount of power. We study the effect that multiple concurrent tasks have on the cache and, subsequently, propose a technique which leverages work on reconfigurable cache architectures to eliminate cache interference and reduce power consumption using application specific information. By mapping parallel tasks to different cache partitions, inter-task interference is completely eliminated with minimal performance impact. Furthermore, both leakage and dynamic power is significantly improved.en_US
dc.format.extent1109590 bytes
dc.titleEliminating Inter-proces Cache Interference Through Reconfigurability for Real-time and Low Power Embedded Systemsen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.contributor.departmentElectrical Engineeringen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledEmbedded Systemsen_US
dc.subject.pquncontrolledReconfigurable Cachesen_US
dc.subject.pquncontrolledLow poweren_US
dc.subject.pquncontrolledCache Partitioning;en_US

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