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VLSI Implemented ML Joint Carrier Phase and Timing Offsets Joint Estimator for QPSK/QQPSK Burst Modems

dc.contributor.advisorBaras, John S.en_US
dc.contributor.authorJiang, Yiminen_US
dc.contributor.authorVerahrami, F.B.en_US
dc.contributor.authorRichmond, R.L.en_US
dc.contributor.authorBaras, John S.en_US
dc.description.abstractA high performance ASIC supporting multiple modulation, error correction, and frame formats is under development at Hughes Network Systems, Inc. Powerful and generic data-aided (DA) estimators are needed to accommodate operation in the required modes. In this paper, a simplified DA maximum likelihood (ML) joint estimator for carrier phase and symbol timing offset for QPSK/OQPSK burst modems and a sample systolic VLSI implementation for the estimator are presented. <p>Furthermore, the Cramer-Rao lower bound (CRLB) for DA case is investigated. The performance of the estimator is shown through simulation to meet the CRLB even at low signal-to-noise ratios (SNR). Compared with theoretical solutions, the proposed estimator is less computationally intensive and is therefore easier to implement using current VLSI technology. IEEE Wireless Communications and Networking Conference: WCNC'99en_US
dc.format.extent244665 bytes
dc.relation.ispartofseriesISR; TR 1999-83en_US
dc.relation.ispartofseriesCSHCN; TR 1999-42en_US
dc.subjectASIC supporting multiple modulationen_US
dc.subjectdata-aided (DA) estimatorsen_US
dc.subjectQPSK/OQPSK burst modemsen_US
dc.subjectCramer-Rao lower bound (CRLB)en_US
dc.subjectGlobal Communication Systemsen_US
dc.titleVLSI Implemented ML Joint Carrier Phase and Timing Offsets Joint Estimator for QPSK/QQPSK Burst Modemsen_US
dc.typeTechnical Reporten_US

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