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ASIC Design of Bit-Serial and Bit-Parallel Discrete Cosine Transform Processors

dc.contributor.advisorLiu, K.J.R.en_US
dc.contributor.authorKarunakaran, Vignarajahen_US
dc.description.abstractDesigns of the bit-serial and bit-parallel versions of the Discrete Cosine Transform Processor using the universal IIR filter module are presented, with emphasis on the bit-serial design. A bit-serial cell mini-library was created. The designs were performed with the AlliedSignal Aerospace Microelectronics Center's 1.2 micro double metal p-well CMOS standard cell library. The core of the bit-serial design is the 18-bit data x 8-bit coefficient bit-serial multiplier, whose design is also presented in detail; the multiplier is capable of handling negative data and negative coefficients, and has an accuracy of o(2-16), The 8-point 18-bit bit-serial DCT has a maximum clock speed of 139.0 MHz and 55.6 MHz under best and worst case conditions respectively. Two bit-parallel design implementations are presented, one with straight bit-parallel multiplier cells and the other with ROM multipliers using distributed arithmetic. The bit-parallel designs are also 8-point, but have an 8-bit wide input and a 12-bit wide output, thereby calculating with much less precision. The parallel multiplier chip's maximum speed under best and worst case conditions is 28.4 MHz and 11.4 MHz respectively, whereas the ROM multiplier chip's is 36.3 MHz and 14.5 MHz respectively. All three designs have a throughput of one clock cycle, with respect to their data input rates. The latencies for the bit-serial and bit-parallel designs are 38 and 5 cycles respectively.en_US
dc.format.extent3267282 bytes
dc.relation.ispartofseriesISR; MS 1994-3en_US
dc.subjectVLSI architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleASIC Design of Bit-Serial and Bit-Parallel Discrete Cosine Transform Processorsen_US

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