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Systolic Architectures for Finite-State Vector Quantization

dc.contributor.authorKolagotla, Ravi K.en_US
dc.contributor.authorYu, S-S.en_US
dc.contributor.authorJaJa, Joseph F.en_US
dc.date.accessioned2007-05-23T09:48:58Z
dc.date.available2007-05-23T09:48:58Z
dc.date.issued1991en_US
dc.identifier.urihttp://hdl.handle.net/1903/5148
dc.description.abstractWe present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. We also present a simple architecture for converting line- scanned image data into the format required by this systolic architecture. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024 x 1024 pixel images at 30 frames/sec in real-time. We describe a VLSI implementation of these FSTSVQ processors.en_US
dc.format.extent757502 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_USen_US
dc.relation.ispartofseriesISR; TR 1991-102en_US
dc.subjectdata compressionen_US
dc.subjectimage processingen_US
dc.subjectsignal processingen_US
dc.subjectspeech processingen_US
dc.subjectvector quantizationen_US
dc.subjectalgorithmsen_US
dc.subjectparallel architecturesen_US
dc.subjectVLSI architecturesen_US
dc.subjectsystolic architecturesen_US
dc.subjectSystems Integrationen_US
dc.titleSystolic Architectures for Finite-State Vector Quantizationen_US
dc.typeTechnical Reporten_US
dc.contributor.departmentISRen_US


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