In this paper, we consider the class of partially symmetric functions and outline a method to realize them. Each such function can be expressed as a sum of totally symmetric functions such that a circuit can be designed whose complexity depends on the size of such symmetric cover. We compare the sizes of symmetric and sum-of-product covers and show that the symmetric cover will be substantially smaller for this class of functions. We also establish bounds on the area required to realize these circuits in a reasonable layout model of VLSI. Our results show that these layouts will be considerably smaller than the corresponding PLA's for the partially symmetric functions.