Search
Now showing items 1-7 of 7
Optimal Unified Architectures for the Real-Time Computation of Time-Recursive Discrete Sinusoidal Transforms
(1993)
An optimal unified architecture that can efficiently compute the Discrete Cosine, Sine, Hartley, Fourier, Lapped Orthogonal, and Complex Lapped transforms for a continuous input data stream is proposed. This structure uses ...
Design and Implementation of Systolic Architectures for Vector Quantization
(1992)
Vector Quantization has emerged as an efficient data compression tool for compressing speech and image data. We develop efficient systolic architecture implementations of Tree-Search Vector Quantizers (TSVQ) and Finite-State ...
VLSI Architectures and Implementation of Predictive Tree- Searched Vector Quantizers for Real-Time Video Compression
(1992)
We describe a pipelined systolic architecture for implementing predictive Tree-Searched Vector Quantization (PTSVQ) for real- time image and speech coding applications. This architecture uses identical processors for both ...
Optimal Unified Architectures for the Real-Time Computation of Time-Recursive Discrete Sinusoidal Transforms
(1992)
An optimal unified architecture that can efficiently compute the Discrete Cosine, Sine, Hartley, Fourier, Lapped Orthogonal, and the Complex Lapped transforms for a continuous input data stream is proposed. This structure ...
VLSI Implementation of Real-Time Parallel DCT/DST Lattice Structures for Video
(1992)
The alternate use [1] of the discrete cosine transform (DCT) and the discrete sine transform (DST) can achieve a higher data compression rate and less block effect in image processing. A parallel lattice structure that can ...
VLSI Implementation of a Tree Searched Vector Quantizer
(1990)
The VLSI design and implementation of a Tree Searched Vector Quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical and data flow between processors is ...
Systolic Architectures for Finite-State Vector Quantization
(1991)
We present a new systolic architecture for implementing Finite State Vector Quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is ...