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Reconfiguration for Programmable ASIC Arrays
In an approach recently proposed for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free ...
This paper provides a detailed review of the state of the art in the field of network reliability analysis. The primary model treated is a stochastic network in which arcs fail randomly and independently with known failure ...
On Designing Parallel Algorithms with Applications to VLSI Routing
Data parallel programming provides a simple and powerful framework for designing parallel algorithms that can be mapped efficiently onto a variety of parallel architectures. The model associates a virtual processor as the ...