Now showing items 1-3 of 3
Co-optimization of TSV assignment and micro-channel placement for 3D-ICs
The three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating ...
TSV-Constrained Micro-Channel Infrastructure Design for Cooling Stacked 3D-ICs
Micro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence ...
Fluidic Cooling and Gate Size Co-optimization in 3D-ICs: Pushing the Power-Performance Limits
The performance improvement of modern computer systems is usually accompanied by increased computational power and thermal hotspots, which in turn limit the further improvement of system performance. In 3D-ICs, this thermal ...