Now showing items 1-4 of 4
An Accurate and Efficient Approach to Statistical Simulation for Large-Scale Analog Circuits
A systematic approach to statistical simulation for large scale analog circuits is presented. The statistical model takes into account mismatch between devices due to variations in the process and noise, as well as interdie ...
The Impact of CD Control on Circuit Yield in Sub-Micron Lithography
As tolerance as a percent of feature size increases for sub- micron technologies with increased scaling, yield loses due to circuit performance fluctuations will increase. Therefore for sub-micron technologies a tradeoff ...
Fault-Driven Testing of LSI Analog Circuits
Analog circuits are usually tested by checking if their specifications are satisfied. This methodology is very costly. We attempt to reduce production testing time by presecuting a fault- driven methodology to handle LSI ...
Yield Optimization for Integrated Circuit
An integrated circuits become increasingly complex, geometries smaller and smaller, it has become more difficult to achieve acceptable manufacturing yield. Four approaches to yield optimization are surveyed and compared. ...