Now showing items 1-4 of 4
System Architecture of a Massively Parallel Programmable Video Co-Processor
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high- performance/low-cost constraints, the state-of-art video processor should be a programmable ...
Algorithm-Based Low-Power Transform Coding Architectures- Part II: Logarithmic Complexity, Unified Architecture, and Finite- Precision Analysis
In the companion paper, we addressed the low-power DCT/IDCT VLSI architectures of linear complexity increase based on the multirate approach. In this paper, we will discuss other aspects of the low-power design. Firstly, ...
Split Recursive Least Squares: Algorithms, Architectures, and Applications
In this paper, a new computationally efficient algorithm for recursive least-squares (RLS) filtering is presented. The proposed Split RLS algorithm can perform the approximated RLS with O(N) complexity for signals having ...
Algorithm-Based Low-Power Transform Coding Architectures- Part I: The multirate Approach
In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In this paper, we propose new ...