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myCACTI: A new cache design tool for pipelined nanometer caches

dc.contributor.advisorJacob, Bruceen_US
dc.contributor.authorRodriguez, Samuelen_US
dc.date.accessioned2007-02-01T20:22:28Z
dc.date.available2007-02-01T20:22:28Z
dc.date.issued2006-11-28en_US
dc.identifier.urihttp://hdl.handle.net/1903/4155
dc.description.abstractTThe presence of caches in microprocessors has always been one of the most important techniques in bridging the memory wall, or the speed gap between the microprocessor and main memory. This importance is continuously increasing especially as we enter the regime of nanometer process technologies (i.e. 90nm and below), as industry has favored investing a larger and larger fraction of a chip.s transistor budget to improving the on-chip cache. This is the case in practice, as it has proven to be an efficient way to utilize the increasing number of transistors available with each succeeding technology. Consequently, it becomes even more important to have cache design tools that give accurate representations of designs that exist in actual microprocessors. The prevalent cache design tools that are the most widely used in academe are CACTI [Wilton1996] and eCACTI [Mamidipaka2004], and these have proven to be very useful tools not just for cache designers, but also for computer architects. This dissertation will show that both CACTI and eCACTI still contain major limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and nanometer caches, especially pipelined designs. These limitations and flaws will be discussed in detail. This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and, in addition, introduces major enhancements to the simulation framework. This dissertation then demonstrates the use of myCACTI in the cache design process. Detailed design space explorations are done on multiple cache configurations to produce pareto optimal curves of the caches to show optimal implementations. Detailed studies are also performed to characterize the delay and power dissipation of different cache configurations and implementations. Finally, future directions to the development of myCACTI are identified to show possible ways that the tool can be improved in such a way as to allow even more different kinds of studies to be performed.en_US
dc.format.extent6785878 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.titlemyCACTI: A new cache design tool for pipelined nanometer cachesen_US
dc.typeDissertationen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.contributor.departmentElectrical Engineeringen_US
dc.subject.pqcontrolledEngineering, Electronics and Electricalen_US
dc.subject.pquncontrolledCacheen_US
dc.subject.pquncontrolledPoweren_US
dc.subject.pquncontrolledEnergyen_US
dc.subject.pquncontrolledMicroprocessoren_US
dc.subject.pquncontrolledNanometer;Memoryen_US


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