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Greedy Coordinate Descent CMP Multi-Level Cache Resizing

dc.contributor.advisorYeung, Donalden_US
dc.contributor.authorChoi, Inseok Stephenen_US
dc.date.accessioned2014-06-24T06:08:58Z
dc.date.available2014-06-24T06:08:58Z
dc.date.issued2014en_US
dc.identifier.urihttp://hdl.handle.net/1903/15327
dc.description.abstractHardware designers are constantly looking for ways to squeeze waste out of architectures to achieve better power efficiency. Cache resizing is a technique that can remove wasteful power consumption in caches. The idea is to determine the minimum cache a program needs to run at near-peak performance, and then reconfigure the cache to implement this efficient capacity. While there has been significant previous work on cache resizing, existing techniques have focused on controlling resizing for a single level of cache only. This sacrifices significant opportunities for power savings in modern CPU hierarchies which routinely employ 3 levels of cache. Moreover, as CMP scaling will likely continue for the foreseeable future, eliminating wasteful power consumption from a CMP multi-level cache hierarchy is crucial to achieve better power efficiency. In this dissertation, we propose a noble technique, greedy coordinate descent CMP multi-level cache resizing, that minimizes a power consumption while maintaining a high performance. We simutaneously resizes all caches in a modern CMP cache hierarchy to minimize the power consumption. Specifically, our approach predicts the power consumption and the performance level without direct evaluations. We also develop greedy coordinate descent method to search an optimal cache configuration utilizing power efficiency gain (PEG) that we propose in this dissertation. This dissertation makes three contributions for a CMP multi-level cache resizing. First, we discover the limits of power savings and performance. This limit study identifies the potential power savings in a CMP multi-level cache hierarchy when wasteful power consumption is eliminated. Second, we propose a prediction-based greedy coordinate descent (GCD) method to find an optimal cache configuration and to orchestrate them. Third, we implement online GCD techniques for a CMP multi-level cache resizing. Our approach exhibits 13.9% power savings and achieves 91% of the power savings of the static oracle cache hierarchy configuration.en_US
dc.language.isoenen_US
dc.titleGreedy Coordinate Descent CMP Multi-Level Cache Resizingen_US
dc.typeDissertationen_US
dc.contributor.publisherDigital Repository at the University of Marylanden_US
dc.contributor.publisherUniversity of Maryland (College Park, Md.)en_US
dc.contributor.departmentElectrical Engineeringen_US
dc.subject.pqcontrolledComputer engineeringen_US
dc.subject.pqcontrolledComputer scienceen_US
dc.subject.pqcontrolledElectrical engineeringen_US
dc.subject.pquncontrolledCache Hiearchyen_US
dc.subject.pquncontrolledComputer Architectureen_US
dc.subject.pquncontrolledCoordinate Descenten_US
dc.subject.pquncontrolledMulti Levelen_US
dc.subject.pquncontrolledPower Efficiencyen_US
dc.subject.pquncontrolledReconfigurableen_US


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