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Co-optimization of TSV assignment and micro-channel placement for 3D-ICs

dc.contributor.advisorAnkur, Srivastava
dc.contributor.authorBing, Shi
dc.contributor.authorAnkur, Srivastava
dc.contributor.authorCaleb, Serafy
dc.description.abstractThe three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating the use of active cooling schemes such as micro-channel liquid coolings. Both TSVs and micro-channels go through the interlayer regions of 3D-IC resulting in potential resource conflict, which deters the optimization of both micro-channel design and TSV allocation/management. This paper investigates the co-optimization of TSV assignment to interlayer nets and micro-channel allocation such that both wirelength and micro-channel cooling energy are co-optimized. We propose a multi-commodity flow based formulation followed by simplifying transformations that enable use of effective polynomial time heuristics. The experimental results show that, our co-optimization approach achieves 46% cooling power savings or 7.6% wire length reduction compared with the approaches that assign TSVs and allocate micro-channels separately.en_US
dc.titleCo-optimization of TSV assignment and micro-channel placement for 3D-ICsen_US
dc.typeTechnical Reporten_US
dc.relation.isAvailableAtInstitute for Systems Researchen_us
dc.relation.isAvailableAtDigital Repository at the University of Marylanden_us
dc.relation.isAvailableAtUniversity of Maryland (College Park, MD)en_us

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