As technology scales deep in submicron regime, CMOS SRAM memories have become increasingly sensitive to Single-Event Upset sensitivity. Key technological factors that impact Single-Event Upset sensitivity are gate length, gate and drain areas and the power supply voltage all of which impact transistor's nodal capacitance. In this work, I present engineering requirement studies, which show for the first time, the tread of Single-Event Upset sensitivity in deeply scaled SRAM cells. To mitigate the Single-Event Upset sensitivity, a novel approach is presented, illustrating exactly how material defects can be managed in a way that sets electrical resistance of the material as desired. A thin-film high-resistance value ranging from 2kΩ/-3.6MΩ/, and TCR of negative 0.0016%/˚C is presented. A defect model is presented that agrees well with the experimental results. These resistors are used in the cross-coupled latches; to decouple the latch nodes and delay the regenerative action of the cell, thus hardening against single even upset (SEU).