A. James Clark School of Engineering

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Author: search.filters.author.Dirik, Cagdas

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    Performance Analysis of NAND Flash Memory Solid-State Disks
    (2009) Dirik, Cagdas; Jacob, Bruce; Electrical Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, Md.)
    As their prices decline, their storage capacities increase, and their endurance improves, NAND Flash Solid-State Disks (SSD) provide an increasingly attractive alternative to Hard Disk Drives (HDD) for portable computing systems and PCs. HDDs have been an integral component of computing systems for several decades as long-term, non-volatile storage in memory hierarchy. Today's typical hard disk drive is a highly complex electro-mechanical system which is a result of decades of research, development, and fine-tuned engineering. Compared to HDD, flash memory provides a simpler interface, one without the complexities of mechanical parts. On the other hand, today's typical solid-state disk drive is still a complex storage system with its own peculiarities and system problems. Due to lack of publicly available SSD models, we have developed our NAND flash SSD models and integrated them into DiskSim, which is extensively used in academe in studying storage system architectures. With our flash memory simulator, we model various solid-state disk architectures for a typical portable computing environment, quantify their performance under real user PC workloads and explore potential for further improvements. We find the following: * The real limitation to NAND flash memory performance is not its low per-device bandwidth but its internal core interface. * NAND flash memory media transfer rates do not need to scale up to those of HDDs for good performance. * SSD organizations that exploit concurrency at both the system and device level improve performance significantly. * These system- and device-level concurrency mechanisms are, to a significant degree, orthogonal: that is, the performance increase due to one does not come at the expense of the other, as each exploits a different facet of concurrency exhibited within the PC workload. * SSD performance can be further improved by implementing flash-oriented queuing algorithms, access reordering, and bus ordering algorithms which exploit the flash memory interface and its timing differences between read and write requests.
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    TERPS: The Embedded Reliable Processing System
    (2005-01) Wang, Hongxia; Rodriguez, Samuel; Dirik, Cagdas; Gole, Amol; Chan, Vincent; Jacob, Bruce
    TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically checkpointing processor state into a special safe-storage device. The detection of EMI invokes rollback, which recovers processor state from a previously check-pointed state and resumes normal execution. Rollback results in loss of performance dictated by the EMI duration; TERPS ensures forward progress of the system provided EMI events are separated by some minimum time interval (e.g., at least 5.12μs for our prototype processor running at 100MHz). The performance overhead of our mechanism is reasonable: 5–6% overhead when checkpointing every 128 processor cycles.
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    Radio Frequency Effects on the Clock Networks of Digital Circuits
    (2004-08) Wang, Hongxia; Dirik, Cagdas; Rodriguez, Samuel V.; Gole, Amol V.; Jacob, Bruce
    Radio frequency interference (RFI) can have adverse effects on commercial electronics. Current properties of high performance integrated circuits (ICs), such as very small feature sizes, high clock frequencies, and reduced voltage levels, increase the susceptibility of these circuits to RFI, causing them to be more prone to smaller interference levels. Also, recent developments of mobile devices and wireless networks create a hostile electromagnetic environment for ICs. Therefore, it is important to measure the susceptibility of ICs to RFI. In this study, we investigate the susceptibility levels to RFI of the clock network of a basic digital building block. Our experimental setup is designed to couple a pulse modulated RF signal using the pin direct injection method. The device under test is an 8-bit ripple counter, designed and fabricated using AMI 0.5 μm process technology. Our experiments showed that relatively low levels of RFI (e.g., 16.8 dBm with carrier frequency of 1 GHz) could adversely affect the normal functioning of the device under test.