Browsing Electrical & Computer Engineering Research Works by Issue Date
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- ItemComposing With Genetic Algorithms(International Computer Music Association, 1995-09) Jacob, BrucePresented is an application of genetic algorithms to the problem of composing music, in which GAs are used to produce a set of data filters that identify acceptable material from the output of a stochastic music generator. The algorithmic composition system variations is described and musical examples of its output are given. Also discussed briefly is the system’s application to microtonal music.
- ItemMagnetic imaging in the presence of external fields: Technique and applications (invited)(American Institute of Physics, 1996-04-15) Gomez, Romel D.; Burke, Edward R.; Mayergoyz, Isaak D.Magnetic force microscopy (MFM) in the presence of an external magnetic field has been developed. This has led to further understanding of image formation in MFM as well as new insights concerning the interaction of magnetic recording media with an external field. Our results confirm that, at low applied fields, image formation results from the interaction of the component by the local surface field along the direction of the probe’s magnetization. By reorienting the probe’s magnetization by an appropriate application of an external field, it is possible to selectively image specific components of the local field. At higher applied fields, the probe becomes saturated and the changes in the images may be attributed to magnetization reversal of the sample. We have observed the transformations that occur at various stages of the dc erasure of thin-film recording media. This technique has also been applied to conventional magneto-optical media to study domain collapse caused by increasing temperature with an external bias field. The methods, results, and their analysis are presented.
- ItemSwitching characteristics of submicron cobalt islands(American Institute of Physics, 1996-07-01) Gomez, R. D.; Shih, M. C.; New, R. M. H.; Pease, R. F. W.; White, R. L.The magnetic characteristics of 0.230.430.02 mm3 cobalt islands were investigated using magnetic force microscopy in the presence of an applied field. The islands were noninteracting and showed a wide variety of single and multidomain configurations. The distribution of magnetization directions supports earlier models which suggest that crystalline anisotropy plays a dominant role in establishing a dispersion of easy axis directions about the long axis of the particles. The magnetic evolution, involving rotation and switching of individual islands, was observed at various points along the microscopic magnetization curve. A magnetization curve of an ensemble of islands was derived from the images and compares remarkably well with macroscopic M–H measurements.
- ItemThe Trading Function in Action(ACM (Association for Computing Machinery) Publications, 1996-09) Jacob, Bruce; Mudge, TrevorThis paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed computing and supports a number of application types on different hardware configurations. This paper is the result of lessons learned in the process of designing, building, and modifying an industrial telecommunications platform. In particular, the use of the trading function in the design of the system led to such benefits as support for the dynamic evolution of the system, the ability to dynamically add services and data types to a running system, support for heterogeneous systems, and a simple design performing well enough to handle traffic in excess of 40,000 busy-hour calls.
- ItemAn Analytical Model for Designing Memory Hierarchies(1996-10) Jacob, Bruce; Chen, Peter M.; Silverman, Seth R.; Mudge, Trevor N.Memory hierarchies have long been studied by many means: system building, trace-driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly size the different levels in a memory hierarchy to a first-order approximation. In this paper, we present a simple analysis for providing this practical help and some unexpected results and intuition that come out of the analysis. By applying a specific, parametized model of workload locality, we are able to derive a closed-form solution for the optimal size of each hierarchy level. We verify the accuracy of this solution against exhaustive simulation with two case studies: a three-level I/O storage hierarchy and a three-level processor-cache hierarchy. In all but one case, the configuration recommended by the model performs within 5% of optimal. One result of our analysis is that the first place to spend money is the cheapest (rather than the fastest) cache level, particularly with small system budgets. Another is that money spent on an n-level hierarchy is spent in a fixed proportion until another level is added.
- ItemAlgorithmic Composition as a Model of Creativity(1996-12) Jacob, Bruce““’There are two distinct types of creativity: the flash out of the blue (inspiration? genius?), and the process of incremental revisions (hard work). Not only are we years away from modeling the former, we do not even begin to understand it. The latter is algorithmic in nature and has been modeled in many systems both musical and non-musical. Algorithmic composition is as old as music composition. It is often considered a cheat, a way out when the composer needs material and/or inspiration. It can also be thought of as a compositional tool that simply makes the composer's work go faster. This article makes a case for algorithmic composition as such a tool. The 'hard work' type of creativity often involves trying many different combinations against each other and choosing one over others. This iterative task seems natural to be expressed as a computer algorithm. The implementation issues can be reduced to two components: how to understand one's own creative process well enough to reproduce it as an algorithm, and how to program a computer to differentiate between 'good' and 'bad' music. The philosophical issues reduce to the question who or what is responsible for the music produced?
- ItemSoftware-Managed Address Translation(1997-02) Jacob, Bruce; Mudge, TrevorIn this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that software-managed address translation is just as efficient as hardware- managed address translation, and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms.
- ItemAnalytical solution for the side-fringing fields of narrow beveled heads(American Institue of Physics, 1997-04-15) Mayergoyz, I. D.; Madabhushi, R.; Burke, E. R.; Gomez, R. D.By using conical coordinates, exact analytical solutions for three-dimensional side-fringing fields of recording heads that are beveled in the down-track direction are found. These solutions are derived under the assumption of zero gap length. The side-fringing fields for the two limiting cases of infinitesimally narrow heads and semi-infinitely wide heads are presented and compared.
- ItemSegmented Addressing Solves the Virtual Cache Synonym Problem(1997-12) Jacob, BruceIf one is interested solely in processor speed, one must use virtually indexed caches. The traditional purported weakness of virtual caches is their inability to support shared memory. Many implementations of shared memory are at odds with virtual caches—ASID aliasing and virtual-address aliasing (techniques used to provide shared memory) can cause false cache misses and/or give rise to data inconsistencies in a virtual cache, but are necessary features of many virtual memory implementations. By appropriately using a segmented architecture one can solve these problems. In this tech report we describe a virtual memory system developed for a segmented microarchitecture and present the following benefits derived from such an organization: (a) the need to flush virtual caches can be eliminated, (b) virtual cache consistency management can be eliminated, (c) page table space requirements can be cut in half by eliminating the need to replicate page table entries for shared pages, and (d) the virtual memory system can be made less complex because it does not have to deal with the virtual-cache synonym problem.
- ItemVirtual Memory in Contemporary Microprocessors(IEEE, 1998) Jacob, Bruce; Mudge, TrevorTHIS SURVEY OF SIX COMMERCIAL MEMORY-MANAGEMENT DESIGNS DESCRIBES HOW EACH PROCESSOR ARCHITECTURE SUPPORTS THE COMMON FEATURES OF VIRTUAL MEMORY: ADDRESS SPACE PROTECTION, SHARED MEMORY, AND LARGE ADDRESS SPACES.
- ItemVirtual Memory: Issues of Implementation(IEEE Computer, 1998-06) Jacob, Bruce; Mudge, TrevorThe authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by implication, how this diversity can complicate and compromise system operations.
- ItemPower Optimization of Variable-Voltage Core-Based Systems(IEEE, 1998-06) Hong, Inki; Kirovski, Darko; Qu, Gang; Potkonjak, Miodrag; Srivastava, Mani B.The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrial-strength multimedia and communication applications.
- ItemQuantification of magnetic force microscopy images using combined electrostatic and magnetostatic imaging(American Institute of Physics, 1998-06-01) Gomez, R. D.; Pak, A. O.; Anderson, A. J.; Burke, E. R.; Leyendecker, A. J.; Mayergoyz, I. D.A method for calibrating the force gradients and probe magnetic moment in phase-contrast magnetic force microscopy ~MFM! is introduced. It is based upon the combined electrostatic force microscopy EFM and MFM images of a conducting non magnetic metal strip. The behavior of the phase contrast in EFM is analyzed and modeled as a finite area capacitor. This model is used in conjunction with the imaging data to derive the proportionality constant between the phase and the force gradient. This calibration is further used to relate the measured MFM images with the field gradient from the same conducting strip to derive the effective magnetic moment of the probe. The knowledge of the phase-force gradient proportionality constant and the probe’s effective moment is essential to directly quantify field derivatives in MFM images.
- ItemTechniques for Energy Minimization of Communication Pipelines(IEEE, 1998-11) Qu, Gang; Potkonjak, Miodrag;The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting factor in many portable systems. We address the problem of how to minimize the power consumption in system-level pipelines under latency constraints. In particular, we exploit advantages provided by variable voltage design methodology to optimally select speed and therefore voltage of each pipeline stage. We define the problem and solve it optimally under realistic and widely accepted assumptions. We apply the obtained theoretical results to develop algorithms for power minimization of computer and communication systems and show that significant power reduction is possible without additional latency.
- ItemAnalysis of Watermarking Techniques for Graph Coloring Problem(IEEE, 1998-11) Qu, Gang; Pokonjak, Miodrag;
- ItemSynthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors(IEEE, 1998-12) Hong, Inki; Qu, Gang; Potkonjak, Miodrag; Srivastava, Mani B.The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-on-a-chip based on core processors, while treating voltage (and correspondingly, the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial since changing the voltage by even a volt may take time equivalent to 100s to 10,000s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of non-linear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine real-life applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.
- ItemSoftware-Managed Caches: Architectural Support for Real-Time Embedded Systems(1998-12) Jacob, Bruce
- ItemQuality of Service and System Design(IEEE, 1999-04) Kornegay, Kevin T.; Qu, Gang; Potkonjak, MiodragQuality of Service (QoS) of the implementation of an application can be defined as a function of the properties of the application and its implementation as observed by the user and/or the environment. Typical application and implementation properties include latency, throughput, jitter, and the level of resolution. Many of the current and pending most popular applications, such as multimedia, wireless sensing and communications, security and PEBBs, have intrinsic relevant QoS components. Recently, quality of service attracted a great of deal of attention in a number of research and development communities, and in particular, in the network and multimedia literature. However, until now synthesis and CAD research did not addressed how to design systems with quantitative QoS requirements. Our goal in this paper is to outline foundations and framework in which QoS system design trade-offs and optimization can be addressed. We first identify and state in synthesis-usable way two currently most popular approaches to Quality of Service treatment: Q-RAM and DScurve (demand/service). We discuss advantages and limitations of the two approaches. Next, we show how these two approaches can be combined in a new more comprehensive QoS framework. We also explain and illustrate using examples interaction between QoS and synthesis and compilation tasks. We conclude by identifying and discussing the future directions related to synthesis of QoS-sensitive systems.
- ItemDomain wall motion in micron-sized Permalloy elements(American Institute of Physics, 1999-04-15) Gomez, R. D.; Luu, T. V.; Pak, O. A.; Mayergoyz, I. D.; Kirk, K. J.; Chapman, J. N.