Browsing by Author "Srivastava, Ankur"

Now showing 1 - 11 of 11
  • Thumbnail Image
    Item
    Dynamic Thermal Management Considering Accurate Temperature-Leakage Interdependency
    (2010-07) Shi, Bing; Srivastava, Ankur; Ankur, Srivastava
    In this paper, we develop an accurate dynamic thermal management DTM approach considering the interdependency of temperature and leakage. By modeling the leakage-thermal interdependence as a quadratic polynomial, we develop accurate analytical equations that capture the thermal transient. We also identify all the situations in which thermal runaway would occur, which should be avoided by DTM.We then present a discrete dynamic programming algorithm that performs thermal-aware task and speed scheduling using the model we derived.Compared to a linear leakage-thermal model, owing to our more accurate model, our scheme resulted in 18.2% better performance while maintaining the temperature below constraint.
  • Thumbnail Image
    Item
    Energy and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing
    (2010) Forte, Domenic; Srivastava, Ankur; Srivastava, Ankur
    Even with consistent advances in storage and transmission capacity, video coding and compression are essential components of multimedia services. Traditional video coding paradigms result in excessive computation at either the encoder or decoder. However, several recent papers have proposed a hybrid PVC/DVC (Predictive/ Distributed Video Coding) codec which shares the video coding workload. In this paper, we propose a controller for such hybrid coders that considers energy and temperature to dynamically split the coding workload of a system comprised of one encoder and one decoder. Results show that the proposed controller results in more balanced energy utilization, improving overall system lifetime and reducing operating temperatures when compared to strictly PVC and DVC systems.
  • Thumbnail Image
    Item
    Fluidic Cooling and Gate Size Co-optimization in 3D-ICs: Pushing the Power-Performance Limits
    (2013) Shi, Bing; Srivastava, Ankur; Srivastava, Ankur
    The performance improvement of modern computer systems is usually accompanied by increased computational power and thermal hotspots, which in turn limit the further improvement of system performance. In 3D-ICs, this thermal problem is significantly exacerbated, necessitating the need for active cooling approaches such as micro-fluidic cooling. This paper investigates a co-optimization approach for 3D-IC electric (gate sizing) and cooling design that fully exploits the interdependency between power, temperature and circuit delay to push the powerperformance tradeoff beyond conventional limits. We propose a unified formulation to model this co-optimization problem and use an iterative optimization approach to solve the problem. The experimental results show a fundamental power-performance improvement, with 12% power saving and 16% circuit speedup.
  • Thumbnail Image
    Item
    Physically Constrained Design Space Modeling for 3D CPUs
    (2015-12) Serafy, Caleb; Srivastava, Ankur; Yeung, Donald; Srivastava, Ankur; Yeung, Donald
    Design space exploration (DSE) is becoming increasingly complex as the number of tunable design parameters increases in cutting edge CPU designs. The advent of 3D integration compounds the problem by expanding the architectural design space, causing intricate links between memory and logic behavior and increasing the interdependence between physical and architectural design. Exhaustive simulation of an architectural design space has become computationally infeasible, and previous work has proposed fast DSE methodologies using modeling or pseudo-simulation. Modeling techniques can be used to predict design space properties by regression fitting. However in the past such techniques have only been applied to optimization metrics such as performance or energy efficiency while physical constraints have been ignored. We propose a technique to apply spline modeling on a 3D CPU design space to predict optimization metrics and physical design properties (e.g. power, area and temperature). We use these models to identify optimal 3D CPU architectures subject to physical constraints while drastically reducing simulation time compared to exhaustive simulation. We show that our technique is able to identify design points within 0.5% of the global optimal while simulating less than 5% of the design space.
  • Thumbnail Image
    Item
    Spintronics-based Reconfigurable Ising Model Architecture
    (2020-03) Mondal, Ankit; Srivastava, Ankur
    The Ising model has been explored as a framework for modeling NP-hard problems, with several diverse systems proposed to solve it. The Magnetic Tunnel Junction (MTJ)-based Magnetic RAM is capable of replacing CMOS in memory chips. In this paper, we propose the use of MTJs for representing the units of an Ising model and leveraging its intrinsic physics for finding the ground state of the system through annealing. We design the structure of a basic MTJ-based Ising cell capable of performing the functions essential to an Ising solver. A technique to use the basic Ising cell for scaling to large problems is described. We then go on to propose Ising-FPGA, a parallel and reconfigurable architecture that can be used to map a large class of NP-hard problems, and show how a standard Place and Route tool can be utilized to program the Ising-FPGA. The effects of this hardware platform on our proposed design are characterized and methods to overcome these effects are prescribed. We discuss how two representative NP-hard problems can be mapped to the Ising model. Simulation results show the effectiveness of MTJs as Ising units by producing solutions close/comparable to the optimum, and demonstrate that our design methodology holds the capability to account for the effects of the hardware.
  • Thumbnail Image
    Item
    Temperature Tracking: An Innovative Run-Time Approach for Hardware Trojan Detection
    (2013-02) Forte, Domenic; Bao, Chongxi; Srivastava, Ankur; Srivastava, Ankur
    The hardware Trojan threat has motivated development of Trojan detection schemes at all stages of the integrated circuit (IC) lifecycle. While the majority of existing schemes focus on ICs at test-time, there are many unique advantages offered by post-deployment/run-time Trojan detection. However, run-time approaches have been underutilized with prior work highlighting the challenges of implementing them with limited hardware resources. In this paper, we propose innovative low-overhead approaches for run-time Trojan detection which exploit the thermal sensors already available in many modern systems to detect deviations in power/thermal profiles caused by Trojan activation. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect active Trojans quickly and with few false positives.
  • Thumbnail Image
    Item
    TimingCamouflage+ Decamouflaged
    (Association for Computer Machinery (ACM), 2023-06-05) Mittu, Priya; Liu, Yuntao; Srivastava, Ankur
    In today’s world, sending a chip design to a third party foundry for fabrication poses a serious threat to one’s intellectual property. To keep designs safe from adversaries, design obfuscation techniques have been developed to protect the IP details of the design. This paper explains how the previously considered secure algorithm, TimingCamouflage+, can be thwarted and the original circuit can be recovered [15]. By removing wave-pipelining false paths, the TimingCamouflage+ algorithm is reduced to the insecure TimingCamouflage algorithm [16]. Since the TimingCamouflage algorithm is vulnerable to the TimingSAT attack, this reduction proves that TimingCamouflage+ is also vulnerable to TimingSAT and not a secure camouflaging technique [7]. This paper describes how wave-pipelining paths can be removed, and this method of handling false paths is tested on various benchmarks and shown to be both functionally correct and feasible in complexity.
  • Thumbnail Image
    Item
    TSV-Constrained Micro-Channel Infrastructure Design for Cooling Stacked 3D-ICs
    (2011-05-11) Shi, Bing; Srivastava, Ankur
    Micro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence of TSVs which form obstacles to the micro-channels prevents distribution of straight micro-channels. In this paper, we investigate the methodology of designing TSV-constrained micro-channel infrastructure. Specifically, we decide the locations and geometry of micro-channels with bended structure so that it's cooling e®ectiveness is maximized. Our micro-channel structure could achieve up to 87% pumping power saving compared with the micro-channel structure using straight channels.
  • Thumbnail Image
    Item
    Unified Datacenter Power Management Considering On-Chip and Air Temperature Constraints
    (2010) Shi, Bing; Srivastava, Ankur; Srivastava, Ankur
    The current approaches for datacenter power management (workload scheduling, CPU speed control, etc) focus primarily on maintaining the air temperature surrounding servers to be within the manufacturer specified constraint. This is problematic since several CPUs may still be violating the on-chip thermal constraint thereby leading to reliability loss. The primary objective of this work is to develop a unified approach for datacenter power optimization (by controlling the CPU speeds) which accounts for both the silicon level temperature of the VLSI components such as CPUs and the air temperature that directly impacts the reliability of other devices such as disks, and also the performance delivered. Our algorithm follows a two step approach: optimally solving a convex approximation that assigns continuous frequency values to all CPUs and a discretization step for legalization of the assigned frequencies. The experimental results indicate that our method guarantees both on-chip CPU and off-chip air temperature to be within temperature constraints. However, the traditional approach of constraining only air temperature will result in on-chip CPU temperature violation on about 40% of the CPUs, or 42% more power consumption to pull the CPU temperature back within constraint by increasing the HVAC cooling.
  • Thumbnail Image
    Item
    Variability Driven Gate Sizing for Binning Yield Optimization
    (2006) Davoodi, Azadeh; Srivastava, Ankur; ISR
  • Thumbnail Image
    Item
    VLSI CAD Tool Protection by Birthmarking Design Solutions
    (IEEE, 2005-04) Yuan, Lin; Qu, Gang; Srivastava, Ankur
    Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem P and a solution S, we want to be able to determine whether S is obtained by a particular tool or algorithm. We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution’s quality. The post-processing technique balances the level of protection and design quality. We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool’s performance.