### Browsing by Author "Qu, Gang"

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Item Achieving Utility Arbitrarily Close to the Optimal with Limited Energy(IEEE, 2000-07) Qu, Gang; Potkonjak, MiodragEnergy is one of the limited resources for modern systems, especially the battery-operated devices and personal digi- tal assistants. The backlog in new technologies for more powerful battery is changing the traditional system design philosophies. For example, due to the limitation on battery life, it is more realistic to design for the optimal benefit from limited resource rather than design to meet all the applica- tions' requirement. We consider the following problem: a system achieves a certain amount of utility from a set of applications by providing them certain levels of quality of service (QoS). We want to allocate the limited system re- sources to get the maximal system utility. We formulate this utility maximization problem, which is NP-hard in gen- eral, and propose heuristic algorithms that are capable of finding solutions provably arbitrarily close to the optimal. We have also derived explicit formulae to guide the alloca- tion of resources to actually achieve such solutions. Simu- lation shows that our approach can use 99.9% of the given resource to achieve 25.6% and 32.17% more system utilities over two other heuristics, while providing QoS guarantees to the application program.Item Analysis of Energy Reduction on Dynamic Scaling-Enabled Systems(IEEE, 2005-12) Yuan, Lin; Qu, GangDynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency, based on the computation load, to provide desired performance with the minimal amount of energy consumption. It has been demonstrated as one of the most effective low power system design techniques, particularly for real time embedded systems. Most existing work are on two different system models that enable DVS: the ideal DVS system that can change its operating voltage with no physical constraints, and the multiple DVS system that has only a number of discrete voltages available. Although the ideal DVS system provides the theoretical lower bound on system’s energy consumption, it is the practicability of multiple DVS systems and the emergence of other DVS-enabled systems, which do not fit either model, that challenges system designers the following questions: should DVS be implemented in the design or not? if so, how should DVS be implemented? In this paper, we answer these questions by studying the DVS-enabled systems that can vary the operating voltage dynamically under various real-life physical constraints. Based on system’s different behavior during voltage transition, we define the optimistic feasible DVS system and the pessimistic feasible DVS system. We buildmathematical model for each DVSenabled system and analyze their potential in energy reduction. Finally, we simulate a secure wireless communication network with different DVS-enabled systems. The results show that DVS gives significant energy saving over system with fixed voltage. Interestingly, we also observe that although multiple DVS system may consume more energy than the theoretical lower bound, the optimistic and pessimistic feasible DVS systems can achieve energy savings very close to the theoretical bound provided by the ideal DVS system.Item Analysis of Watermarking Techniques for Graph Coloring Problem(IEEE, 1998-11) Qu, Gang; Pokonjak, Miodrag;Item Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages(IEEE, 2003-11) Hua, Shaoxiong; Qu, Gang;Dynamic voltage scaling (DVS) is arguably the most effective energy reduction technique. The multiple-voltage DVS systems, which can operate only at pre-determined discrete voltages, are practical and have been well studied. However, one important unsolved problem is how many levels and at which values should voltages be implemented on a multiple-voltage DVS system to achieve the maximum energy saving. We refer this as the voltage set-up problem. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For the general case that does not have analytic solutions, we develop efficient numerical methods. (3) We demonstrate how to apply the proposed algorithms on system design. (4) Interestingly, the experimental results suggest that the multiple-voltage DVS system, when the voltages are set up properly, can reach DVS technique’s full potential in energy saving. Specifically, on the design of an ad hoc application specific system and the design of the MPEG video encoder, we find that the best single-voltage systems consume 150% and 20% more energy than the tight theoretical lower bounds, respectively. However, our approach gives dual-, 3-, and 4-voltage DVS system settings that are only 17.6%, 4.9%, and 2.6% for the ad hoc system, and 4.0%, 1.1%, and 0.2% for the MPEG video encoder, over the same lower bounds.Item ARBITRATE-AND-MOVE PRIMITIVES FOR HIGH THROUGHPUT ON-CHIP INTERCONNECTION NETWORKS(IEEE, 2004-05) Balkan, Aydin O.; Vishkin, U.; Qu, GangAn n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga- Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.Item The Associative-Skew Clock Routing Problem(IEEE, 1999-11) Chen, Yu; Kahng, Andrew B.; Qu, Gang; Zelikovsky, AlexanderWe introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative skew problem is easier to address within current EDA frameworks than useful-skew (skew-scheduling) approaches, and defines an interesting tradeoff between the traditional zero-skew clock routing problem (one sink group) and the Steiner minimum tree problem (n sink groups). We present a set of heuristic building blocks, including an efficient and optimal method of merging two zero-skew trees such that zero skew is preserved within the sink sets of each tree. Finally, we list a number of open issues for research and practical application.Item CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems(IEEE, 2005-07) Kianzad, Vida; Bhattacharyya, Shuvra S.; Qu, GangFor multiprocessor embedded systems, the dynamic voltage scaling (DVS) technique can be applied to scheduled applications for energy reduction. DVS utilizes slack in the schedule to slow down processes and save energy. Therefore, it is generally believed that the maximal energy saving is achieved on a schedule with the minimum makespan (maximal slack). Most current approaches treat task assignment, scheduling, and DVS separately. In this paper, we present a framework called CASPER (Combined Assignment, Scheduling, and PowER-management) that challenges this common belief by integrating task scheduling and DVS under a single iterative optimization loop via genetic algorithm. We have conducted extensive experiments to validate the energy efficiency of CASPER. For homogeneous multiprocessor systems (in which all processors are of the same type), we consider a recently proposed slack distribution algorithm (PDP-SPM) [3]: applying PDP-SPM on the schedule with the minimal makespan gives an average of 53.8% energy saving; CASPER finds schedules with slightly larger makespan but a 57.3% energy saving, a 7.8% improvement. For heterogeneous systems, we consider the power variation DVS (PV-DVS) algorithm [13], CASPER improves its energy efficiency by 8.2%. Finally, our results also show that the proposed single loop CASPER framework saves 23.3% more energy over GMA+EE-GLSA [12], the only other known integrated approach with a nested loop that combines scheduling and power management in the inner loop but leaves assignment in the outer loop.Item A Combined Gate Replacement and Input Vector Control Approach(2005-11-10T18:38:48Z) Yuan, Lin; Qu, GangDue to the increasing role of leakage power in CMOS circuit's total power dissipation, leakage reduction has attracted a lot of attention recently. Input vector control (IVC) takes advantage of the transistor stack effect to apply the minimum leakage vector (MLV) to the primary inputs of the circuit during the standby mode. However, IVC techniques become less effective for circuits of large logic depth because theMLV at primary inputs has little impact on internal gates at high logic level. In this paper, we propose a technique to overcome this limitation by directly controlling the inputs to the internal gates that are in their worst leakage states. Specifically, we propose a gate replacement technique that replaces such gates by other library gates while maintaining the circuit's correct functionality at the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction, when the MLV is not effective. We then describe a divideand- conquer approach that combines the gate replacement and input vector control techniques. It integrates an algorithm that finds the optimal MLV for tree circuits, a fast gate replacement heuristic, and a genetic algorithm that connects the tree circuits. We have conducted experiments on all the MCNC91 benchmark circuits. The results reveal that 1) the gate replacement technique itself can provide 10% more leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; 3) when we obtain the optimal MLV for small circuits from exhaustive search, the proposed gate replacement alone can still reduce leakage current by 13% while the divide-and-conquer approach reduces 17%.Item A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction(IEEE, 2006-02) Yuan, Lin; Qu, GangInput vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit’s correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.Item Design Space Exploration for Energy-Efficient Secure Sensor Network(IEEE, 2002-07) Yuan, Lin; Qu, GangWe consider two of the most important design issues for distributed sensor networks in the battlefield: security for communication in such hostile terrain; and energy efficiency because of battery’s limited capacity and the impracticality of recharging. Communication security is normally provided by encryption, i.e., data are encrypted before transmission and will be decrypted first on reception. We exploit the secure sensor network design space for energy efficiency by investigating different microprocessors coupled with various public key algorithms. We propose a power control mechanism for sensors to operate at an energy-efficient fashion using the newly developed dynamical voltage scaling (DVS) technique. In particular, we consider multiple voltage processors and insert additional information into the communication channel to guide the selection of proper voltages for data decryption/encryption and processing in order to reduce the total computational energy consumption. We experiment several encryption standards on a broad range of embedded processors and simulate the behavior of the sensor network to show that the sensor’s lifetime can be extended substantially.Item Dual-Processor Design of Energy Efficient Fault-Tolerant System(IEEE, 2006-09) Hua, Shaoxiong; Pari, Pushkin R.; Qu, GangA popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the comple- tion of the primary copy. If there is no fault, the sec- ondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual- processor system. Specifically, we first derive an opti- mal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system’s energy con- sumption at run time by taking advantage of the actual execution time which is less than the WCET. Simula- tion on real-life benchmark applications shows that our technique can save up to 80% energy while still provid- ing fault tolerance.Item Effective Iterative Techniques for Fingerprinting Design IP(IEEE, 1999-06) Caldwell, Andrew E.; Choi, Hyun-Jin; Kahng, Andrew B.; Mantik, Stefanus; Potkonjak, Miodrag; Qu, Gang; Wong, Jennifer L.While previous watermarking-based approaches to intellectual property protection (IPP) have asymmetrically emphasized the IP provider’s rights, the true goal of IPP is to ensure the rights of both the IP provider and the IP buyer. Symmetric fingerprinting schemes have been widely and effectively used to achieve this goal; however, their application domain has been restricted only to static artifacts, such as image and audio. In this paper, we propose the first generic symmetric fingerprinting technique which can be applied to an arbitrary optimization/synthesis problem and, therefore, to hardware and software intellectual property. The key idea is to apply iterative optimization in an incremental fashion to solve a fingerprinted instance; this leverages the optimization effort already spent in obtaining a previous solution, yet generates a uniquely fingerprinted new solution. We use this approach as the basis for developing specific fingerprinting techniques for four important problems in VLSI CAD: partitioning, graph coloring, satisfiability, and standard-cell placement. We demonstrate the effectiveness of our fingerprinting techniques on a number of standard benchmarks for these tasks. Our approach provides an effective tradeoff between runtime and resilience against collusion.Item Effective Iterative Techniques for Fingerprinting Design IP(IEEE, 2004-01) Caldwell, Andrew E.; Choi, Hyun-Jin; Kahng, Andrew B.; Mantik, Stefanus; Potkonjak, Miodrag; Qu, Gang; Wong, Jennifer L.Fingerprinting is an approach that assigns a unique and invisible ID to each sold instance of the intellectual property (IP). One of the key advantages fingerprinting-based intellectual property protection (IPP) has over watermarking-based IPP is the enabling of tracing stolen hardware or software. Fingerprinting schemes have been widely and effectively used to achieve this goal; however, their application domain has been restricted only to static artifacts, such as image and audio, where distinct copies can be obtained easily. In this paper, we propose the first generic fingerprinting technique that can be applied to an arbitrary synthesis (optimization or decision) or compilation problem and, therefore to hardware and software IPs. The key problem with design IP fingerprinting is that there is a need to generate a large number of structurally unique but functionally and timing identical designs. To reduce the cost of generating such distinct copies, we apply iterative optimization in an incremental fashion to solve a fingerprinted instance. Therefore, we leverage on the optimization effort already spent in obtaining previous solutions, yet we generate a uniquely fingerprinted new solution. This generic approach is the basis for developing specific fingerprinting techniques for four important problems in VLSI CAD: partitioning, graph coloring, satisfiability, and standard-cell placement. We demonstrate the effectiveness of the new fingerprinting-based IPP techniques on a number of standard benchmarks.Item Energy Minimization of System Pipelines Using Multiple Voltages(IEEE, 1999-05) Qu, Gang; Kirovski, Darko; Potkonjak, Miodrag; Srivastava, Mani B.Modem computer and communication system design has to consider the timing constraints imposed by communication and system pipelines, and minimize the energy consumption. We adopt the recent proposed model for communication pipeline latency[23] and address the problem of how to minimize the power consumption in system-level pipelines under the latency constraints by selecting supply voltage for each pipeline stage using the variable voltage core-based system design methodology[l 11. We define the problem, solve it optimally under realistic assumptions and develop algorithms for power minimization of system pipeline designs based on our theoretical results. We apply this new approach on the 4- stage Myrinet GAM pipeline, with the appropriate voltage profiles, we achieve 93.4%, 91.3% and 26.9% power reduction on three pipeline stages over the traditional design.Item Energy Minimization with Guaranteed Quality of Service(IEEE, 2000-07) Qu, Gang; Potkonjak, Potkonjak; Copyright © 2000 IEEE. Reprinted from ACM/IEEE International Symposium on Low Power Electronics and Dsign. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Maryland's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.Quality of service (QoS) is one of the key features for new Internet-based multimedia and other applications. Mean- while, energy remains as a big concern for systems that per- form such applications. We address the issue of combining system design concerns and QoS requirements to design systems that can deliver QoS guarantees. In this paper, we discuss how to satisfy QoS requirements and minimize the system's energy consumption. Specifically, we consider the following problem: Given a set of applications each specifying its required amount of computation and service time, how we allocate CPU time and determine the voltage profile on a variable voltage system, such that all the applications' requirements are satisfied and the system's total energy con- sumption is minimized. We optimally solve several basic cases and propose a dynamic programming procedure for the general case. Simulation shows that the new approach saves 38.75% energy over the system shut-down technique.Item Energy Reduction Techniques for Multimedia Applications with Tolerance to Deadline Misses(IEEE, 2003-06) Hua, Shaoxiong; Qu, Gang; Bhattacharyya, Shuvra S.Many embedded systems such as PDAs require processing of the given applications with rigid power budget. However, they are able to tolerate occasional failures due to the imperfect human visual/auditory systems. The problem we address in this paper is how to utilize such tolerance to reduce multimedia system’s energy consumption for providing guaranteed quality of service at the user level in terms of completion ratio. We explore a range of offline and on-line strategies that take this tolerance into account in conjunction with the modest non-determinism in application’s execution time. First, we give a simple best-effort approach that achieves the maximum completion ratio; then we propose an enhanced on-line best-effort energy minimization (BEEM) approach and a hybrid offline/on-line minimumeffort (O2ME) approach. We prove that BEEM maintains the maximum completion ratio while consuming the provably least amount of energy and O2ME guarantees the required completion ratio statistically. We apply both approaches to a variety of benchmark task graphs, most from popular DSP applications. Simulation results show that significant energy savings (38% for BEEM and 54% for O2ME, both over the simple best-effort approach) can be achieved while meeting the required completion ratio requirements.Item Exploring the Probabilistic Design Space of Multimedia Systems(IEEE, 2003-06) Hua, Shaoxiong; Qu, Gang; Bhattacharyya, Shuvra S.In this paper, we propose the novel concept of probabilistic design for multimedia systems and a methodology to quickly explore such design space at an early design stage. The probabilistic design is motivated by the challenge of how to design, but not over-design, multimedia embedded systems while systematically incorporating such application’s performance requirements, uncertainties in execution time, and tolerance for reasonable execution failures. Our goal is to bridge the gap between real-time analysis and embedded software implementation for rapid and economic (multimedia) system prototyping. Our method takes advantage of multimedia system’s unique features mentioned above to relax the rigid hardware requirements for software implementation and eventually avoid over-designing the system.Item Fair Watermarking Techniques(IEEE, 2000-01) Qu, Gang; Wong, Jennifer L.; Potkonjak, MiodragMany intellectual property protection (IPP) techniques have been proposed. Their primary objectives are providing convincible proof of authorship with least degradation of the quality of the intellectual property (IP), and achieving robustness against attacks. These are also well accepted as the most important criteria to evaluate different IPP techniques. The essence of such techniques is to limit the solution space by embedding signatures as constraints. One key issue that should be addressed but has not been discussed is the fairness of the techniques: what is the quality of the solution subspace for different signatures, that is, how large the solution subspace is (uniqueness), and how difficulty it is to get a solution from such subspace (hardness)? In this paper, we introduce fairness as one of the metrics for good IPP techniques and post the challenge problem of how to design fair watermarking techniques. We claim that all fair techniques have to be instanceoriented and due to the complexity of the problem itself, we propose an approach that utilizes the statistical information of the problem instance. We use the satisfiability (SAT) problem as an example to illustrate how fairness could be achieved. We make the observation that the unfairness of the previous watermarking techniques comes from the global embedding of the signature and propose fair watermarking techniques. We test the uniqueness and hardness on a model with full knowledge of the solution and real life benchmarks as well. The experimental results show fairness can be achieved.Item Fingerprinting Intellectual Property Using Constraint-Addition(IEEE, 2000-06) Qu, Gang; Potkonjak, MiodragRecently, intellectual property protection (IPP) techniques attracted a great deal of attention from semiconductor, system integration and software companies. A number of watermarking-based techniques have been proposed for IPP. One of the key limitations of watermarking is that it does not facilitate tracing of illegally resold intellectual property (IP). Fingerprinting resolves this problem by providing each customer with a unique instance of functionally identical IP. We propose a general technique which enables fingerprinting at all level of design process and is applicable to an arbitrary optimization step. In particular, we address the following fingerprinting problem: How to generate a large number of high quality solution for a given optimization problem by solving the initial problem only once. In addition we also discuss how to select a subset of k solutions from the pool of n solutions so that the solutions are maximally different. In order to make our discussion concrete we focus on a single NP-complete problem - graph coloring. We test the new fingerprinting on a number of standard benchmarks. Interestingly, while on random graphs it is relatively difficult to produce a large number of solutions without nontrivial quality degradation, on all real-life compilation graphs we are able to generate millions of solution which are all optimal.Item An FSM Re-Engineering Approach to Sequential Circuit Synthesis by State Splitting(2008) Lin, Yuan; Qu, Gang; Villa, Tiziano; Sangiovanni-Vincentelli, AlbertoWe propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to re-construct a functionally equivalent but topologically different FSM based on the optimization objective, and concludes with another round of FSM synthesis on the re-constructed FSM. This approach explores a larger solution space that consists of a set of FSMs functionally equivalent to the original one, making it possible to obtain better solutions than in the original FSM. Guided by the result from the rst round of synthesis, the solution space exploration process can be rapid and cost-ef cient. We apply this framework to FSM state encoding for power minimization and area minimization. The FSM is rst minimized and encoded using existing state encoding algorithms. Then we develop both a heuristic algorithm and a genetic algorithm to re-construct the FSM. Finally, the FSM is reencoded by the same encoding algorithms. To demonstrate the effectiveness of this framework, we conduct experiments on MCNC91 sequential circuit benchmarks. The circuits are read in and synthesized in SIS environment. After FSM re-engineering are performed, we measure the power, area and delay in the newly synthesized circuits. In the powerdriven synthesis, we observe an average 5.5% of total power reduction with 1.3% area increase and 1.3% delay increase. This results are in general better than other low power state encoding techniques on comparable cases. In the area-driven synthesis, we observe an average 2.7% area reduction, 1.8% delay reduction, and 0.4% power increase. Finally, we use integer linear programming to obtain the optimal low power state encoding for benchmarks of small size. We nd that the optimal solutions in the re- engineered FSMs are 1% to 8% better than the optimal solutions in the original FSMs in terms of power minimization.

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