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|Title: ||VLSI CAD Tool Protection by Birthmarking Design Solutions|
|Authors: ||Yuan, Lin|
|Issue Date: ||Apr-2005|
|Citation: ||L. Yuan, G. Qu, and A. Srivastava. "VLSI CAD Tool Protection by Birthmarking Design Solutions," 15th IEEE /ACM Great Lakes Symposium on VLSI (GLSVLSI'05), pp. 341-344, April 2005.|
|Abstract: ||Many techniques have been proposed in the past for the protection
of VLSI design IPs (intellectual property). CAD tools and algorithms
are intensively used in all phases of modern VLSI designs;
however, little has been done to protect them. Basically, given
a problem P and a solution S, we want to be able to determine
whether S is obtained by a particular tool or algorithm.
We propose two techniques that intentionally leave some trace or
birthmark, which refers to certain easy detectable properties, in the
design solutions to facilitate CAD tool tracing and protection. The
pre-processing technique provides the ideal protection at the cost of
losing control of solution’s quality. The post-processing technique
balances the level of protection and design quality.
We conduct a case study on how to protect a timing-driven gate
duplication algorithm. Experimental results on a large set of MCNC
benchmarks confirm that the pre-processing technique results in
a significant reduction (about 48%) of the optimization power of
the tool, while the post-processing technique has almost no penalty
(less than 2%) on the tool’s performance.|
|Required Publisher Statement: ||Copyright © 2005 IEEE. Reprinted from 15th IEEE/ACM Great Lakes Symposium on VLSI.
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|Appears in Collections:||Electrical & Computer Engineering Research Works|
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