Run-Time Instruction Cache Configurability For Energy Efficiency In Embedded Multitasking Workloads
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In this thesis we propose a methodology for energy reduction in multitasking computing systems by addressing the energy consumption of the on-chip instruction cache. Our technique leverages recently introduced reconfigurable cache technology to partition the instruction cache at run-time using application specific profile information. Each application is given a sub-section of the cache as its partition which alone is kept active while the corresponding application is executed. The remaining inactive sections are kept in a low-power mode, reducing both dynamic and leakage power. Isolating tasks into disjoint cache partitions also results in eliminating or drastically reducing inter-task I-cache interference. No prior information about the timing of the tasks within the workload is required. In some cases, partitions may be required to overlap, which could degrade performance because of cache interference in the overlapped region. For such cases we propose and evaluate run-time partition update policies which trade-off the power savings to ensure guaranteed performance.