In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes down. In this paper, we propose new algorithmic-level techniques for compensating the increased delays based on the multirate approach. We present two methods, the Chebyshev polynomial approach and the polyphase decomposition approach, to design low- power but high-speed transform coding architectures. We will show how to compute the discrete cosine transform (DCT) and its inverse (IDCT) through the decimated low-speed sequences with reasonable linear hardware overhead. For the case the decimation factor equal to two, the overall power consumption can be reduced to about one-third of the original design at the architectural level. Extension of our design to higher decimation rate is also achievable and can result in even lower power consumption. The resulting multirate low-power architectures are regular, modular, and free of global communications. Also, the compensation capability is achieved at the expense of locally increased hardware and data paths. As a consequence, they are very suitable for VLSI implementation. The proposed architectures can also be applied to very high-speed block transforms where only low-speed operators are required. The extensions of the algorithm-based low-power design, such as the unified transform architecture and finite-wordlength effect of the design, will be discussed in the companion paper.