Discrete Cosine Transform (DCT) based compression techniques play an important role in today's digital applications such as high definition television (HDTV) and teleconferencing which require high speed transmission of digital video signals. In this thesis, a high-performance VLSI implementation of a DSP chip which computes the two-dimensional discrete cosine transform and its inverse (2-D DCT/IDCT) is presented. The chip is based on the fully-pipelined time recursive IIR structure and employs a highly modular and hierarchical design strategy. Architectural model simulations are performed for determining system parameters required to achieve a high-speed and high-performance implementation. Based on these simulations, ROM and internal bus precision are chosen to ensure a minimum PSNR of 40 dB which is required for most digital imaging applications. High speed design is obtained by using distributed arithmetic to achieve fast multiplication through table lookups. A two-phase nonoverlapping clock is employed to perform computations in both phases, resulting in twice the throughput. Various submodules like ROM lookup tables. adders, half-latches, delay-units and multiplexors are implemented. Timing simulations of critical path modules indicate a clock frequency of 50 MHz corresponding to a data rate of 400 Mb/s. The chip dimensions are 24550 l x 27094 l and its area is 240 mm2. The chip has been submitted for fabrication in 1.2 CMOS N-well double-metal single-poly technology.