A general scheme for the VLSI implementation of auditory wavelet transforms is proposed using switched-capacitor (SC) circuits. SC circuits are well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by both capacitor ratios and the clock frequency. The hardware implementations are made possible by several new circuit designs. Specifically, extremely area-efficient designs are presented to implement very large time-constant filters such as those used to process speech and other acoustic signals. the designs employ a new charge differencing technique to reduce significantly the capacitance spread ratios needed in the filter banks. Also, a new sum-gain amplifier (SGA-SI) is designed which permits several inputs to be sampled with the same phase. The proposed circuits have been fabricated using a 1 m CMOS double-poly process. Preliminary data and performance measures of the circuits are very encouraging and are presented. Two possible architectures for implementing the wavelet transform are discussed and compared: parallel and cascade filter banks. Responses of both filter banks are simulated using SWITCAP-II. Finally, we shall also briefly discuss the utility, from an implementation point of view, of decomposing the transfer functions of the filter banks into rational form using a recently-developed wavelet system (WS) technique.