In this dissertation the basic techniques for designing more sophisticated adaptive array systems are first developed. Then several systolic architectures based on numerically stable and computationally efficient algorithms are proposed for adaptive array systems. Compared to the existing architectures proposed elsewhere in the literature, our new systolic architectures are more efficient structures for real-time signal processing applications and VLSI hardware implementation. The reasons are (1) the proposed systolic architectures are based on numerically stable and computationally efficient systolic algorithms, (2) there is no bottleneck in the whole architecture since QR decomposition by the square root free fast Givens method is used, (3) the whole architecture has a fully pipelined design since backward substitution is avoided, (4) it is a single fully pipelined open-loop system without any feedback arrangement, and (5) the systolic architectures function recursively to update the result for each new snapshot. Therefore, the new VLSI systolic architectures proposed in this dissertation using QR-recursive least squares (QR-RLS) and QR-constrained recursive least squares (QR-CRLS) techniques archieve minimal memory and maximal parallelism for real-time signal processing applications and VLSI hardware implementation.