Analog-to-digital converters form the backbone of many real world systems. A compression and expansion (companding) capability is a useful tool to increase the signal-to-noise ratio of many of these applications. Frequently, power-signal systems utilize analog compression to simplify signal processing. A novel compressing high-speed converter is presented in this thesis. The converter described here has a natural compressing transfer function of f(x)=1-1/x. The converter is a variation on Flash conversion, so it is high speed, with a sampling frequency of 80MHz. A four bit implementation of this converter was manufactured on a 0.5μm CMOS process with an area of 0.018mm2. The power consumed was 50mW on a first pass design. The compressing converter will to scale with process improvements. The converter desensitizes the linear region to reference mismatch, and arbitrary compressing transfer functions can be obtained.