http://hdl.handle.net/1903/1654 Wed, 19 Jun 2013 00:06:37 GMT 2013-06-19T00:06:37Z http://drum.lib.umd.edu:80/retrieve/42373/_logo_umlibraries.jpg http://hdl.handle.net/1903/1654 http://hdl.handle.net/1903/13945 Title: REU: Improving straight line travel in a miniature wheeled robot Authors: Gessler, Katie; Sabelhaus, Andrew Abstract: The TinyTeRP is a miniature robotics platform with modular sensing capabilities. Prior generations of the TinyTeRP have experienced various problems in assembly process, materials selection, and their fundamental design. These problems are addressed by choosing 3D printing as the new manufacturing method and steel wire for the new axle. The TinyTeRP’s ability to travel in a straight line using open loop control is studied. After 1.37 m of travel in the x direction, the TinyTeRP was as close as 4.69 cm to or as far as 31.9 cm from the ideal ending position (a straight line), indicating that open loop control is a poor method for controlling a straight line trajectory. Comparing data on the angle of the trajectory collected from position data from the vision table to data collected from the gyroscope indicated that the gyroscope tracks the robot’s angle of motion well. Hence, using the gyroscope for closed loop control of the TinyTeRP’s motion is possible. Fri, 10 Aug 2012 00:00:00 GMT http://hdl.handle.net/1903/13945 2012-08-10T00:00:00Z http://hdl.handle.net/1903/13893 Title: XMTSim: A Simulator of the XMT Many-core Architecture Authors: Keceli, Fuat; Vishkin, Uzi Abstract: This paper documents the features and the design of XMTSim, the cycle-accurate simulator of the Explicit Multi-Threading (XMT) computer architecture. The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. XMTSim is a primary component in its publicly available toolchain along with an optimizing compiler. Research and experimentation enabled by the toolchain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer's workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the goal of ease-of-programming and performance. The applicability of the XMT simulator extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the toolchain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Sat, 01 Jan 2011 00:00:00 GMT http://hdl.handle.net/1903/13893 2011-01-01T00:00:00Z http://hdl.handle.net/1903/13890 Title: Empirical Speedup Study of Truly Parallel Data Compression Authors: Edwards, James A.; Vishkin, Uzi Abstract: We present an empirical study of novel work-optimal parallel algorithms for Burrows-Wheeler compression and decompression of strings over a constant alphabet. To validate these theoretical algorithms, we implement them on the experimental XMT computing platform developed especially for supporting parallel algorithms at the University of Maryland. We show speedups of up to 25x for compression, and 13x for decompression, versus bzip2, the de facto standard implementation of Burrows-Wheeler compression. Unlike existing approaches, which assign an entire (e.g., 900KB) block to a processor that processes the block serially, our approach is “truly parallel” as it processes in parallel the entire input. Besides the theoretical interest in solving the “right” problem, the importance of data compression speed for small inputs even at great expense of quality (compressed size of data) is demonstrated by the introduction of Google’s Snappy for MapReduce. Perhaps surprisingly, we show feasibility of holding on to quality, while even beating Snappy on speed. In turn, this work adds new evidence in support of the XMT/PRAM thesis: that an XMT-like many-core hardware/ software platform may be necessary for enabling general-purpose parallel computing. Comparison of our results to recently published work suggests 70x improvement over what current commercial parallel hardware can achieve. Sat, 20 Apr 2013 00:00:00 GMT http://hdl.handle.net/1903/13890 2013-04-20T00:00:00Z http://hdl.handle.net/1903/13872 Title: Design and testing methodologies for signal processing systems using DICE Authors: Kedilaya, Soujanya Akirebari Abstract: The design and integration of embedded systems in heterogeneous programming environments is still largely done in an ad hoc fashion making the overall development process more complicated, tedious and error-prone. In this work, we propose enhancements to existing design flows that utilize model-based design to verify cross-platform correctness of individual actors. The DSPCAD Integrative Command Line Environment (DICE) is a realization of managing these enhancements. We demonstrate this design flow with two case studies. By using DICE's novel test framework on modules of a triggering system in the Large Hadron Collider, we demonstrate how the cross-platform model-based approach, automatic testbench creation and integration of testing in the design process alleviate the rigors of developing such a complex digital system. The second case study is an exploration study into the required precision for eigenvalue decomposition using the Jacobi algorithm. This case study is a demonstration of the use of dataflow modeling in early stage application exploration and the use of DICE in the overall design flow. Fri, 01 Jan 2010 00:00:00 GMT http://hdl.handle.net/1903/13872 2010-01-01T00:00:00Z